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The sync_instruction_memory() function performs whatever steps are required to make instructions modified by a program executable.
Some processor architectures, including some SPARC processors, have separate and independent instruction and data caches which are not kept consistent by hardware. For example, if the instruction
cache contains an instruction from some address and the program then stores a new instruction at that address, the new instruction may not be immediately visible to the instruction fetch mechanism. Software
must explicitly invalidate the instruction cache entries for new or changed mappings of pages that might contain executable instructions. The sync_instruction_memory() function performs
this function, and/or any other functions needed to make modified instructions between addr and addr+len visible. A program should call sync_instruction_memory() after modifying instructions and before executing them.
On processors with unified caches (one cache for both instructions and data) and pipelines which are flushed by a branch instruction, such as the Intel IA architecture, the function may do nothing
and just return.
The changes are immediately visible to the thread calling sync_instruction_memory() when the call returns, even if the thread should migrate to another processor during or after
the call. The changes become visible to other threads in the same manner that stores do; that is, they eventually become visible, but the latency is implementation-dependent.
The result of executing sync_instruction_memory() are unpredictable if addr through addr+len-1 are not valid
for the address space of the program making the call.
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