5.3 Floating-Point Instruction

Table 5-4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.

Table 5-4

SPARC	Mnemonic¹	Argument List	Description
`FiTOs`	`fitos`	freg_rs2, freg_rd	Convert integer to single
`FiTOd`	`fitod`	freg_rs2, freg_rd	Convert integer to double
`FiTOq`	`fitoq`	freg_rs2, freg_rd	Convert integer to quad
`FsTOi`	`fstoi`	freg_rs2, freg_rd	Convert single to integer
`FdTOi`	`fdtoi`	freg_rs2, freg_rd	Convert double to integer
`FqTOi`	`fqtoi`	freg_rs2, freg_rd	Convert quad to integer
`FsTOd`	`fstod`	freg_rs2, freg_rd	Convert single to double
`FsTOq`	`fstoq`	freg_rs2, freg_rd	Convert single to quad
`FdTOs`	`fdtos`	freg_rs2, freg_rd	Convert double to single
`FdTOq`	`fdtoq`	freg_rs2, freg_rd	Convert double to quad
`FqTOd`	`fqtod`	freg_rs2, freg_rd	Convert quad to double
`FqTOs`	`fqtos`	freg_rs2, freg_rd	Convert quad to single
`FMOVs`	`fmovs`	freg_rs2, freg_rd	Move
`FNEGs`	`fnegs`	freg_rs2, freg_rd	Negate
`FABSs`	`fabss`	freg_rs2, freg_rd	Absolute value
`FSQRTs` `FSQRTd` `FSQRTq`	`fsqrts` `fsqrtd` `fsqrtq`	freg_rs2, freg_rd freg_rs2, freg_rd freg_rs2, freg_rd	Square root
`FADDs` `FADDd` `FADDq`	`fadds` `faddd` `faddq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Add
`FSUBs` `FSUBd` `FSUBq`	`fsubs` `fsubd` `fsubq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Subtract
`FMULs` `FMULd` `FMULq`	`fmuls` `fmuld` `fmulq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Multiply
`FdMULq`	`fmulq`	freg_rs1, freg_rs2, freg_rd	Multiply double to quad
`FsMULd`	`fsmuld`	freg_rs1, freg_rs2, freg_rd	Multiply single to double
`FDIVs` `FDIVd` `FDIVq`	`fdivs` `fdivd` `fdivq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Divide
`FCMPs` `FCMPd` `FCMPq`	`fcmps` `fcmpd` `fcmpq`	freg_rs1, freg_rs2 freg_rs1, freg_rs2 freg_rs1, freg_rs2	Compare
`FCMPEs` `FCMPEd` `FCMPEq`	`fcmpes` `fcmped` `fcmpeq`	freg_rs1, freg_rs2 freg_rs1, freg_rs2 freg_rs1, freg_rs2	Compare, generate exception if not ordered

¹ Types of Operands are denoted by the following lower-case letters:i integers singled doubleq quad

5.4 Coprocessor Instructions

All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. The data types supported by the coprocessor are coprocessor-dependent. Operand alignment is also coprocessor-dependent. Coprocessor-operate instructions are described in Table 5-5.

If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0, or if a coprocessor is not present, a cpopn instruction causes a cp_disabled trap.

The conditions that cause a cp_exception trap are coprocessor-dependent.

Table 5-5

SPARC	Mnemonic	Argument List	Name	Comments
`CPop1`	`cpop1`	opc, reg_rs1, reg_rs2, reg_rd	Coprocessor operation
`CPop2`	`cpop2`	opc, reg_rs1, reg_rs2, reg_rd	Coprocessor operation	May modify `ccc`

5.5 Synthetic Instructions

Table 5-6 describes the mapping of synthetic instructions to hardware instructions.

Table 5-6

Synthetic Instruction		Hardware Equivalent(s)		Comment
`btst`	reg_or_imm, reg_rs1	`andcc`	reg_rs1, reg_or_imm, `%g0`	Bit test
`bset`	reg_or_imm, reg_rd	`or`	reg_rd, reg_or_imm, reg_rd	Bit set
`bclr`	reg_or_imm, reg_rd	`andn`	reg_rd, reg_or_imm, reg_rd	Bit clear
`btog`	reg_or_imm, reg_rd	`xor`	reg_rd, reg_or_imm, reg_rd	Bit toggle
`call`	reg_or_imm	`jmpl`	reg_or_imm, `%o7`
`clr`	reg_rd	`or`	`%g0`, `%g0`, reg_rd	Clear (zero) register
`clrb`	[address]	`stb`	`%g0`, [address]	Clear byte
`clrh`	[address]	`st`	`%g0`, [address]	Clear halfword
`clr`	[address]	`st`	`%g0`, [address]	Clear word
`cmp`	reg, reg_or_imm	`subcc`	reg_rs1, reg_or_imm, `%g0`	Compare
`dec`	reg_rd	`sub`	reg_rd, 1, reg_rd	Decrement by 1
`dec`	const13, reg_rd	`sub`	reg_rd, const13, reg_rd	Decrement by const13
`deccc`	reg_rd	`subcc`	reg_rd, 1, reg_rd	Decrement by 1 and set `icc`
`deccc`	const13, reg_rd	`subcc`	reg_rd, const13, reg_rd	Decrement by const13 and set `icc`
`inc`	reg_rd	`add`	reg_rd, 1, reg_rd	Increment by 1
`inc`	const13, reg_rd	`add`	reg_rd, const13, reg_rd	Increment by const13
`inccc`	reg_rd	`addcc`	reg_rd, 1, reg_rd	Increment by 1 and set `icc`
`inccc`	const13, reg_rd	`addcc`	reg_rd, const13, reg_rd	Increment by const13 and set `icc`
`jmp`	address	`jmpl`	address, `%g0`
`mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov`	reg_or_imm,reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 reg_or_imm, `%y` reg_or_imm, `%psr` reg_or_imm, `%wim` reg_or_imm, `%tbr`	`or` `rd` `rd` `rd` `rd` `wr` `wr` `wr` `wr`	`%g0`, reg_or_imm, reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 `%g0`,reg_or_imm,`%y` `%g0`,reg_or_imm,`%psr` `%g0`,reg_or_imm,`%wim` `%g0`,reg_or_imm,`%tbr`
`not`	reg_rs1, reg_rd	`xnor`	reg_rs1, `%g0`, reg_rd	One's complement
`not`	reg_rd	`xnor`	reg_rd, `%g0`, reg_rd	One's complement
`neg`	reg_rs1, reg_rd	`sub`	`%g0`, reg_rs2, reg_rd	Two's complement
`neg`	reg_rd	`sub`	`%g0`, reg_rd, reg_rd	Two's complement
`restore`		`restore`	`%g0`, `%g0`, `%g0`	Trivial restore
`save`		`save`	`%g0`, `%g0`, `%g0`	Trivial save trivial save should only be used in supervisor code!
`set`	value,reg_rd	`or`	`%g0`, value, reg_rd	if -4096 <=value <= 4095 Do not use the `set` synthetic instruction in an instruction delay slot.
`set`	value,reg_rd	`sethi`	`%hi`(value), reg_rd	if ((value & 0x3ff) == 0)
`set`	value, reg_rd	`sethi` `or`	`%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd	otherwise Do not use the `set` synthetic instruction in an instruction delay slot.
`skipz`		`bnz,a .+8`		if z is set, ignores next instruction
`skipnz`		`bz,a .+8`		if z is not set, ignores next instruction
`tst`	reg	`orcc`	reg_rs1, `%g0`, `%g0`	test

5.6 V8/V9 Natural Pseudo Instructions

Table 5-7 describes the V8/V9 natural pseudo instructions that will help increase the portability of your assembly code from V8/V8plus to V9.

Table 5-7

Pseudo Instructions	-xarch=
Pseudo Instructions	V8/V8plus¹	V9
`ldn`	ld	ldx
`stn`	`st`	stx
`ldna`	lda	ldxa
`stna`	`sta`	stxa
`setn`	set	`setx`
setnhi	sethi	setxhi
casn	cas	casx
slln	sll	sllx
srln	srl	srlx
sran	sra	srax
clrn	clr	clrx

¹ Indicates default setting

Note - Depending on the value set for the -xarch option, the assembler substitutes the appropriate pseudo instruction.