InfoDoc ID   Synopsis   Date
40760   Dtag parity error explained   19 Oct 2001

Status Issued

Description 
The DT_PERR indicates a Duplicate Tag SRAM (DTAG) parity error.
These DTAG SRAMs reside on the CPU/Memory boards.  Dtags are duplicates of the CPU's Etags on the board.      
Note that DT_PERRA refers to DTAG SRAMs at CPU location 0 and DT_PERRB refers to DTAG SRAMs at CPU location 1.      
Again, these DTAG SRAMs reside on the CPU/Memory Board, not on the CPU Module themselves so, in this example, the CPU/MEM Board in slot 2 should be replaced. The CPUs and memory on this board are still good.      
Example of a Dtag parity error:      
17-OCT-2001 17:07:55.17 LBC5   Fatal Reset      
17-OCT-2001 17:07:56.69 LBC5   0,0>FATAL ERROR      
17-OCT-2001 17:07:57.15 LBC5   0,0>     At time of error: System software was running.      
17-OCT-2001 17:07:57.37 LBC5   0,0>     Diagnosis: Board 2, Dtag B (UPA Port1),AC      
17-OCT-2001 17:07:57.37 LBC5   0,0>Log Date: Oct 17 21:17:19 GMT 2001 17-OCT-2001 17:07:57.37 LBC5   0,0>      
17-OCT-2001 17:07:57.58 LBC5   0,0>RESET INFO for CPU/Memory  board in slot 2      
17-OCT-2001 17:07:57.58 LBC5   0,0>     AC ESR 00000010.00000000 DT_PERRB      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[0] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[1] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[2] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[3] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[4] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[5] 00      
17-OCT-2001 17:07:57.59 LBC5   0,0>     DC[6] 00      
17-OCT-2001 17:07:57.80 LBC5   0,0>     DC[7] 00      
17-OCT-2001 17:07:57.80 LBC5   0,0>     FHC  CSR 00050030 LOC_FATAL SYNC BRD_LED_M BRD_LED_R      
17-OCT-2001 17:07:57.80 LBC5   0,0>     FHC RCSR 02000000  FATAL      
17-OCT-2001 17:07:57.80 LBC5   0,0> Config policy change      
17-OCT-2001 17:07:57.80 LBC5   0,0>      
17-OCT-2001 17:07:57.80 LBC5   0,0>@(#) POST 3.9.28 2000/12/20 12:29      
17-OCT-2001 17:07:58.02 LBC5   0,0>Copyright 2000 Sun Microsystems, Inc. All rights reserved.      
17-OCT-2001 17:07:58.02 LBC5   0,0>      
17-OCT-2001 17:07:58.03 LBC5       SelfTest Initializing (Diag Level 10, ENV 0000ff01) IMPL 0011 MASK 20      
17-OCT-2001 17:07:58.03 LBC5   0,0>Board 0 CPU FPROM Test 17-OCT-2001 17:07:58.24 LBC5   0,0>Board 0 Basic CPU Test      
17-OCT-2001 17:07:58.25 LBC5   0,0>    Set CPU UPA Config and Init SDB Data      
17-OCT-2001 17:07:58.25 LBC5   0,0>     SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0      
17-OCT-2001 17:07:58.25 LBC5   0,1>Board 0 CPU FPROM Test      
17-OCT-2001 17:07:58.37 LBC5   0,0>Board 0 MMU EnaCPU Test      
17-OCT-2001 17:07:58.37 LBC5   0,0>    DMMU Init      
17-OCT-2001 17:07:58.45 LBC5   0,1>    Set CPU UPA Config and Init SDB Data      
17-OCT-2001 17:07:58.45 LBC5   0,0>    IMMU Init      
17-OCT-2001 17:07:58.53 LBC5   0,1>     SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0      
17-OCT-2001 17:07:58.53 LBC5   0,0>    Mapping Selftest Enabling MMUs      
17-OCT-2001 17:07:58.78 LBC5   0,1>Board 0 MMU Enable Test      
17-OCT-2001 17:07:58.78 LBC5   0,1>    DMMU Init      
17-OCT-2001 17:07:58.78 LBC5   0,0>Board 0 Ecache Test      
17-OCT-2001 17:07:58.78 LBC5   0,0>    Ecache Probe      
17-OCT-2001 17:07:58.78 LBC5   0,1>    IMMU Init      
17-OCT-2001 17:07:58.99 LBC5   0,0>    Ecache Tags      
17-OCT-2001 17:07:58.99 LBC5   0,1>    Mapping Selftest Enabling MMUs      
17-OCT-2001 17:07:59.00 LBC5   0,1>Board 0 Ecache Test      
17-OCT-2001 17:07:59.00 LBC5   0,1>    Ecache Probe      
17-OCT-2001 17:07:59.00 LBC5   0,1>    Ecache Tags      
17-OCT-2001 17:08:00.14 LBC5   0,0>    Ecache Quick Verify      
17-OCT-2001 17:08:31.96 LBC5   0,1>    Ecache Quick Verify      
17-OCT-2001 17:08:31.99 LBC5   0,0>    Ecache Init      
17-OCT-2001 17:08:57.48 LBC5   0,1>    Ecache Init      
17-OCT-2001 17:08:57.99 LBC5   0,0>    Ecache RAM      
17-OCT-2001 17:09:06.84 LBC5   0,1>    Ecache RAM      
17-OCT-2001 17:09:06.99 LBC5   0,0>    Ecache Address Line      
17-OCT-2001 17:09:08.20 LBC5   0,0>    Configure Ecache Limit      
17-OCT-2001 17:09:08.21 LBC5   0,0>Ecache Size = 00400000,  Limited to 00400000      
17-OCT-2001 17:09:08.28 LBC5   0,0>Board 0 FPU Functional Test      
17-OCT-2001 17:09:08.29 LBC5   0,0>    FPU Enable      
17-OCT-2001 17:09:08.29 LBC5   0,1>    Ecache Address Line      
17-OCT-2001 17:09:08.36 LBC5   0,0>Board 0 Board Master Select Test      
17-OCT-2001 17:09:08.37 LBC5   0,0>    Selecting a Board Master      
17-OCT-2001 17:09:08.44 LBC5   0,1>    Configure Ecache Limit      
17-OCT-2001 17:09:08.45 LBC5   0,0>Board 0 FireHose Devices Test      
17-OCT-2001 17:09:08.52 LBC5   0,1>Ecache Size = 00400000,  Limited to 00400000      
17-OCT-2001 17:09:08.53 LBC5   0,1>Board 0 FPU Functional Test      
17-OCT-2001 17:09:08.60 LBC5   0,1>    FPU Enable      
17-OCT-2001 17:09:08.61 LBC5   0,1>Board 0 Board Master Select Test      
17-OCT-2001 17:09:08.61 LBC5   0,1>    Selecting a Board Master      
17-OCT-2001 17:09:08.68 LBC5   0,0>Board 0 Address Controller Test      
17-OCT-2001 17:09:08.69 LBC5   0,0>    AC Initialization      
17-OCT-2001 17:09:08.76 LBC5   0,0>    AC DTAG Init      
17-OCT-2001 17:09:08.99 LBC5   0,0>Board 0 Dual Tags Test      
17-OCT-2001 17:09:09.64 LBC5   0,0>    AC DTAG Init      
17-OCT-2001 17:09:09.99 LBC5   0,0>Board 0 FireHose Controller Test      
17-OCT-2001 17:09:10.60 LBC5   0,0>    FHC Initialization      
17-OCT-2001 17:09:10.61 LBC5   0,0>Board 0 JTAG Test      
17-OCT-2001 17:09:10.61 LBC5   0,0>    Verify System Board Scan Ring      
17-OCT-2001 17:09:10.68 LBC5   0,0>Board 0 Centerplane Test      
17-OCT-2001 17:09:10.69 LBC5   0,0>    Centerplane Join      
17-OCT-2001 17:09:10.76 LBC5   0,0>Setting JTAG Master      
17-OCT-2001 17:09:10.84 LBC5   0,0>Clear JTAG Master      
17-OCT-2001 17:09:10.99 LBC5   0,0>Board 0 Setup Cache Size Test      
17-OCT-2001 17:09:17.40 LBC5   0,0>    Setting Up Cache Size      
17-OCT-2001 17:09:17.40 LBC5   0,0>Board 0 System Master Select Test      
17-OCT-2001 17:09:17.48 LBC5   0,0>    Setting System Master      
17-OCT-2001 17:09:17.48 LBC5   0,0>POST Master Selected (JTAG,CENTRAL)      
17-OCT-2001 17:09:17.56 LBC5   0,0>Board 16 Clock Board Test      
17-OCT-2001 17:09:17.56 LBC5   0,0>    Clock Board Initialization      
17-OCT-2001 17:09:17.64 LBC5   0,0>    Clock Board Temperature Check      
17-OCT-2001 17:09:17.65 LBC5   0,0>Board 16 Clock Board Serial Ports Test      
17-OCT-2001 17:09:17.72 LBC5   0,0>Board 16 NVRAM Devices Test      
17-OCT-2001 17:09:17.73 LBC5   0,0>    M48T59 (TOD) Init      
17-OCT-2001 17:09:17.73 LBC5   0,0>Board 0 System Board Probe  Test      
17-OCT-2001 17:09:17.80 LBC5   0,0>    Probing all CPU/Memory BDA      
17-OCT-2001 17:09:17.81 LBC5   0,0>    Probing System Boards      
17-OCT-2001 17:09:17.88 LBC5   0,0>    Probing CPU Module JTAG Rings      
17-OCT-2001 17:09:17.96 LBC5   0,0>Setting System Clock Frequency      
17-OCT-2001 17:09:17.99 LBC5   0,0>     CPU Module mid 0 Checked in OK (speed code = 7)      
17-OCT-2001 17:09:18.05 LBC5   0,0>     CPU mid 1 Version=00170011.20000507      
17-OCT-2001 17:09:18.12 LBC5   0,0>     CPU Module mid 1 Checked in OK (speed code = 7)      
17-OCT-2001 17:09:18.13 LBC5   0,0>     CPU mid 4 Version=00170011.20000507      
17-OCT-2001 17:09:18.20 LBC5   0,0>     CPU Module mid 4 Checked in OK (speed code = 7)      
17-OCT-2001 17:09:18.28 LBC5   0,0>     CPU mid 5 Version=00170011.20000507      
17-OCT-2001 17:09:18.28 LBC5   0,0>     CPU Module mid 5 Checked in OK (speed code = 7)      
17-OCT-2001 17:09:18.36 LBC5   0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336      
17-OCT-2001 17:09:18.44 LBC5   0,0>WARNING Board 2 is disabled by bad Hardware      
17-OCT-2001 17:09:18.52 LBC5   0,0>WARNING Setting Board 2 to Low Power Mode      
17-OCT-2001 17:09:18.60 LBC5   0,0>TESTING BOARD 1      
17-OCT-2001 17:09:18.60 LBC5   0,0>Board 1 JTAG Test      
17-OCT-2001 17:09:18.68 LBC5   0,0>    Verify System Board Scan Ring      
17-OCT-2001 17:09:18.76 LBC5   0,0>Board 1 Centerplane Test      
17-OCT-2001 17:09:18.76 LBC5   0,0>    Centerplane Check      
17-OCT-2001 17:09:18.99 LBC5   0,0>Board 1 Address Controller Test      
17-OCT-2001 17:09:19.01 LBC5   0,0>    AC Initialization      
17-OCT-2001 17:09:19.01 LBC5   0,0>Setting Freq to 25MHZ      
17-OCT-2001 17:09:19.08 LBC5   0,0>    AC DTAG Init      
17-OCT-2001 17:09:19.11 LBC5   0,0>Board 1 FireHose Controller Test      
17-OCT-2001 17:09:19.16 LBC5   0,0>    FHC Initialization      
17-OCT-2001 17:09:19.17 LBC5   0,0>Board 1 NVRAM Devices Test      
17-OCT-2001 17:09:19.17 LBC5   0,0>    M48T59 (TOD) Init      
17-OCT-2001 17:09:19.24 LBC5   0,0>TESTING BOARD 3      
17-OCT-2001 17:09:19.24 LBC5   0,0>Board 3 JTAG Test      
17-OCT-2001 17:09:19.25 LBC5   0,0>    Verify System Board Scan Ring      
17-OCT-2001 17:09:19.32 LBC5   0,0>Board 3 Centerplane Test      
17-OCT-2001 17:09:19.40 LBC5   0,0>    Centerplane Check      
17-OCT-2001 17:09:19.56 LBC5   0,0>Board 3 Address Controller Test      
17-OCT-2001 17:09:19.56 LBC5   0,0>    AC Initialization      
17-OCT-2001 17:09:19.64 LBC5   0,0>Setting Freq to 25MHZ      
17-OCT-2001 17:09:19.64 LBC5   0,0>    AC DTAG Init      
17-OCT-2001 17:09:19.72 LBC5   0,0>Board 3 FireHose Controller Test      
17-OCT-2001 17:09:19.73 LBC5   0,0>    FHC Initialization      
17-OCT-2001 17:09:19.73 LBC5   0,0>Board 3 NVRAM Devices Test      
17-OCT-2001 17:09:19.80 LBC5   0,0>    M48T59 (TOD) Init      
17-OCT-2001 17:09:19.80 LBC5   0,0>Re-mapping to Local Device Space      
17-OCT-2001 17:09:19.88 LBC5   0,0>Begin Central Space Serial Port access      
17-OCT-2001 17:09:19.88 LBC5   0,0>Enable AC Control Parity      
17-OCT-2001 17:09:19.96 LBC5   0,0>Hotplug Trigger Test      
17-OCT-2001 17:09:19.96 LBC5   0,0>Init Counters for Hotplug      
17-OCT-2001 17:09:19.97 LBC5   0,0>Board 0 Cross Calls Test      
17-OCT-2001 17:09:19.99 LBC5   0,0>Board 0 Environmental Probe Test      
17-OCT-2001 17:09:20.05 LBC5   0,0>    Environmental Probe      
17-OCT-2001 17:09:20.12 LBC5   0,0>Checking Power Supply Configuration      
17-OCT-2001 17:09:20.20 LBC5   0,0>Power is more than adequate, load 3 ps 4      
17-OCT-2001 17:09:20.20 LBC5   0,0>Reconfig memory due to FATAL RESET      
17-OCT-2001 17:09:20.42 LBC5   0,0>Reconfig memory due to new CONFIG POLICY      
17-OCT-2001 17:09:20.42 LBC5   0,0>Board 0 Probing Memory SIMMS Test      
17-OCT-2001 17:09:20.42 LBC5   0,0>    Probe SIMMID      
17-OCT-2001 17:09:20.63 LBC5   0,0>     Populated Memory Bank Status      
17-OCT-2001 17:09:20.64 LBC5   0,0>             bd #    Size    Address Way Status      
17-OCT-2001 17:09:20.64 LBC5   0,0>             0       1024 Normal      
17-OCT-2001 17:09:20.64 LBC5   0,0>             0       1024 Normal      
17-OCT-2001 17:09:20.64 LBC5   0,0>Board 0 Memory Configuration Test      
17-OCT-2001 17:09:20.64 LBC5   0,0>    Memory Interleaving      
17-OCT-2001 17:09:20.64 LBC5   0,0>     Total banks with 8MB SIMMs = 0      
17-OCT-2001 17:09:20.85 LBC5   0,0>     Total banks with 32MB SIMMs = 0      
17-OCT-2001 17:09:20.85 LBC5   0,0>     Total banks with 128MB SIMMs = 2      
17-OCT-2001 17:09:20.85 LBC5   0,0>     Total banks with 256MB SIMMs = 0      
17-OCT-2001 17:09:20.85 LBC5   0,0>     Overall memory default speed = 60ns      
17-OCT-2001 17:09:20.85 LBC5   0,0>Do OPTIMAL INTLV      
17-OCT-2001 17:09:21.07 LBC5   0,0>     Board 0 AC rev 5 RCTIME = 0 (Tras 71)      
17-OCT-2001 17:09:21.07 LBC5   0,0>     Board 0 AC rev 5 RCTIME = 0 (Tras 71)      
17-OCT-2001 17:09:21.07 LBC5   0,0>    Memory Refresh Enable      
17-OCT-2001 17:09:21.28 LBC5   0,0>Board 0 SIMMs Test      
17-OCT-2001 17:09:21.28 LBC5   0,0>TESTING IO BOARD 1      
17-OCT-2001 17:09:21.28 LBC5   0,0>Board 1 I/O FPROM Test      
17-OCT-2001 17:09:21.28 LBC5   0,0>@(#) iPOST 3.4.28 2000/12/20 12:28      
17-OCT-2001 17:09:21.28 LBC5   0,0> TESTING IO BOARD 1 ASICs      
17-OCT-2001 17:09:21.28 LBC5   0,0> TESTING SysIO Port 0      
17-OCT-2001 17:09:21.51 LBC5   0,0>Board 1 SysIO Registers Test      
17-OCT-2001 17:09:21.51 LBC5   0,0>    SysIO Register Initialization      
17-OCT-2001 17:09:21.51 LBC5   0,0>    SysIO RAM Initialization      
17-OCT-2001 17:09:21.51 LBC5   0,0>Board 1 SysIO Functional Test      
17-OCT-2001 17:09:21.76 LBC5   0,0>    Clear Interrupt Map and State Registers      
17-OCT-2001 17:09:21.77 LBC5   0,0>Board 1 OnBoard IO Chipset (SOC) Test      
17-OCT-2001 17:09:21.78 LBC5   0,0> TESTING SysIO Port 1      
17-OCT-2001 17:09:21.78 LBC5   0,0>Board 1 SysIO Registers Test      
17-OCT-2001 17:09:21.78 LBC5   0,0>    SysIO Register Initialization      
17-OCT-2001 17:09:21.78 LBC5   0,0>    SysIO RAM Initialization      
17-OCT-2001 17:09:21.89 LBC5   0,0>Board 1 SysIO Functional Test      
17-OCT-2001 17:09:21.97 LBC5   0,0>    Clear Interrupt Map and State Registers      
17-OCT-2001 17:09:21.97 LBC5   0,0>Board 1 OnBoard IO Chipset (FEPS) Test      
17-OCT-2001 17:09:21.97 LBC5   0,0>IO BOARD 1 TESTED      
17-OCT-2001 17:09:21.99 LBC5   0,0>TESTING IO BOARD 3      
17-OCT-2001 17:09:22.05 LBC5   0,0>Board 3 I/O FPROM Test      
17-OCT-2001 17:09:22.12 LBC5   0,0>@(#) iPOST 3.4.28 2000/12/20 12:28      
17-OCT-2001 17:09:22.13 LBC5   0,0> TESTING IO BOARD 3 ASICs      
17-OCT-2001 17:09:22.13 LBC5   0,0> TESTING SysIO Port 0      
17-OCT-2001 17:09:22.21 LBC5   0,0>Board 3 SysIO Registers Test      
17-OCT-2001 17:09:22.21 LBC5   0,0>    SysIO Register Initialization      
17-OCT-2001 17:09:22.28 LBC5   0,0>    SysIO RAM Initialization      
17-OCT-2001 17:09:22.29 LBC5   0,0>Board 3 SysIO Functional Test      
17-OCT-2001 17:09:22.37 LBC5   0,0>    Clear Interrupt Map and State Registers      
17-OCT-2001 17:09:22.41 LBC5   0,0>Board 3 OnBoard IO Chipset (SOC) Test      
17-OCT-2001 17:09:22.45 LBC5   0,0> TESTING SysIO Port 1      
17-OCT-2001 17:09:22.45 LBC5   0,0>Board 3 SysIO Registers Test      
17-OCT-2001 17:09:22.52 LBC5   0,0>    SysIO Register Initialization      
17-OCT-2001 17:09:22.53 LBC5   0,0>    SysIO RAM Initialization      
17-OCT-2001 17:09:22.60 LBC5   0,0>Board 3 SysIO Functional Test      
17-OCT-2001 17:09:22.60 LBC5   0,0>    Clear Interrupt Map and State Registers      
17-OCT-2001 17:09:22.68 LBC5   0,0>Board 3 OnBoard IO Chipset (FEPS) Test      
17-OCT-2001 17:09:22.68 LBC5   0,0>IO BOARD 3 TESTED      
17-OCT-2001 17:09:22.76 LBC5   0,0>Probing for Disk System boards      
17-OCT-2001 17:09:22.76 LBC5   0,0>Board 0 System Interrupts Test      
17-OCT-2001 17:09:22.77 LBC5   0,0>POST Failed      
17-OCT-2001 17:09:22.84 LBC5   0,0>      
17-OCT-2001 17:09:22.84 LBC5   0,0>     System Board Status      
17-OCT-2001 17:09:22.92 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:22.99 LBC5   0,0> Slot   Board Status     Board Type Failures      
17-OCT-2001 17:09:23.01 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:23.08 LBC5   0,0>  0  | Normal         | CPU/Memory  |      
17-OCT-2001 17:09:23.16 LBC5   0,0>  1  | Normal         |+IO Type 4   |      
17-OCT-2001 17:09:23.16 LBC5   0,0>  2  | Low Power Mode | CPU/Memory  | AC DTags1      
17-OCT-2001 17:09:23.24 LBC5   0,0>  3  | Normal         |+IO Type 4   |      
17-OCT-2001 17:09:23.24 LBC5   0,0>  4  | Not installed  |             |      
17-OCT-2001 17:09:23.32 LBC5   0,0>  5  | Not installed  |             |      
17-OCT-2001 17:09:23.33 LBC5   0,0>  6  | Not installed  |             |      
17-OCT-2001 17:09:23.40 LBC5   0,0>  7  | Not installed  |             |      
17-OCT-2001 17:09:23.48 LBC5   0,0> 16  | Normal         | Clock Board |      
17-OCT-2001 17:09:23.56 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:23.56 LBC5   0,0>      
17-OCT-2001 17:09:23.57 LBC5   0,0>     CPU Module Status      
17-OCT-2001 17:09:23.64 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:23.64 LBC5   0,0> MID  OK  Cache  Speed   Version      
17-OCT-2001 17:09:23.72 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:23.80 LBC5   0,0>  0 | y | 4096  |  336  | 00170011.20000507      
17-OCT-2001 17:09:23.88 LBC5   0,0>  1 | y | 4096  |  336  | 00170011.20000507      
17-OCT-2001 17:09:23.96 LBC5 0,0>-----------------------------------------------------------------      
17-OCT-2001 17:09:23.99 LBC5   0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336      
17-OCT-2001 17:09:24.05 LBC5   0,0>     Populated Memory Bank Status      
17-OCT-2001 17:09:24.12 LBC5   0,0>             bd #    Size    Address Way Status      
17-OCT-2001 17:09:24.12 LBC5   0,0>             0       1024    0       2 Normal      
17-OCT-2001 17:09:24.20 LBC5   0,0>             0       1024    1       2 Normal      
17-OCT-2001 17:09:24.20 LBC5   0,0>      
17-OCT-2001 17:09:24.99 LBC5   0,0>      
17-OCT-2001 17:09:29.88 LBC5    POST COMPLETE      
17-OCT-2001 17:09:30.10 LBC5   0,0>Entering OBP      
17-OCT-2001 17:09:41.99 LBC5   8-slot Sun Enterprise 4000/5000, No Keyboard      
...
INTERNAL SUMMARY:

Created doc from technical email by Saaid Magidi and Tong-Pheng Koh

SUBMITTER: Gary Northup APPLIES TO: Hardware, Hardware/Ultra Enterprise, Hardware/Sun Fire ATTACHMENTS:

Copyright (c) 1997-2003 Sun Microsystems, Inc.