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The clock sources that are available for primary and secondary clock selection are:
The PXM1 supports either a Stratum 3 or Stratum 4 enhanced clock.
The internal clock meets the Stratum 3 and Stratum 4 requirements as detailed in Table 10-1 and Table 10-2.
| Accuracy | Holdover Stability | Pull in Range |
4.6xe-6 | 1xe-8/day | 4.6xe-6 |
| Accuracy | Holdover Stability | Pull in Range |
32x10-6 | no holdover | 32x10-6 |
The MGX 8250 guarantees an 8 kHz clock speed during the time it switches over to other sources.
The MGX 8250 clock synchronization system meets the following criteria as specified Bellcore GR-1244-CORE, Section 2.6
The MGX 8250 also supports clock synchronization system redundancy in compliance to GR-1244-CORE, Section 3.3
The MGX 8250 accepts external timing from T1 and E1 interfaces. The PXM User Interface card that resides in the upper service bay provides the T1/E1 timing reference ports:


The E1 interface on the PXM back card has been designed to support both options according to G.703. As per G.703 table 6, it supports an unframed HDB3 E1 (2048 KBps) signal. According to G.703 table 10 (now called table 11), it also supports a timing signal of 2048 kHz.
GX 8250 is capable of the following external timing and formats:
The MGX 8250 edge concentrator is capable of receiving a minimum of two external timing references on separate physical interfaces. These are provisioned as the active (act) and alternate (alt). The terms act and alt are interchangeable depending on which reference is active, and providing timing reference for the system. The system also provides a DS1 reference for external timing in D4 (SF) format. At least two DS1 synchronization references, as specified in Bellcore GR-1244-CORE, Section 3.4, can be configured.
A switchover from the active clock source (primary or secondary) to the standby clock source will occur when the hardware detects a failure that warrants a switchover. The currently selected clock source is constantly monitored by the hardware to ensure that it is within tolerance.
If a failure in this selected clock is detected, the hardware gracefully switches over to the secondary clock source specified.
If both the primary and secondary sources have failed, the hardware will automatically output the clock generated internally on the card. Once the primary clock is within tolerance, the hardware will automatically switch back to it.
Regardless of whether the clock switchover is initiated by the user or by the hardware, the switchover meets the Accunet T1.5 Maximum Time Interval Error (MTIE) specification.
When all timing references fail, as specified in Bellcore GR-1244-CORE, Section 3.4.1, the MGX 8250 can operate in self-timing, or free-running mode, using an internal clock.
The external clock input is revertive, whereas any other clock source (PXM line or AUSM/CESM line) is nonrevertive.
The MGX 8250 recognizes the following DS1 impairments or conditions as failures:
Alarms are generated when a synchronization source, either active or standby, fails for some reason. Clocking failures do not affect any configuration or settings on either the PXM 1 or PXM45.
Switch software upgrades do not cause changes in timing sources. A Y-cable is used to connect the external clock associated with both the active and standby processor cards. Part of the normal switch software upgrade process is a PXM switchover, the Y-cable will ensure clocking integrity to the external source.
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Posted: Mon Oct 2 17:00:46 PDT 2000
Copyright 1989-2000©Cisco Systems Inc.