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This chapter discusses the following two Fast Ethernet (FE) interface processors:
In this chapter, combined and mutually applicable references to the FEIP and FEIP2 are referred to as FEIP, with specific differences between the FEIP and FEIP2 clearly noted.
![]() | Caution To prevent system problems, do not exchange FEIP interfaces with FEIP2 interfaces. |
The FEIP is a fixed-configuration interface processor that provides up to two, IEEE 802.3u, 100BASE-T Fast Ethernet (FE) interfaces. (See Figure 6-1.) The FEIP is available in the following four fixed configurations:
(An equal sign [=] indicates the entire FEIP assembly is available as a spare part.)
Each FE interface on an FEIP can be configured at 100 Mbps, half duplex or full duplex, for a maximum aggregate bandwidth of 200 Mbps.
![]() | Caution To prevent oversubscribing the FEIP, we recommend that you do not operate both FE interfaces on an FEIP in full-duplex mode. |
The FEIP uses a Reduced Instructions Set Computing (RISC), MIPS 4600 processor for high performance, and has an internal operating frequency of 100 megahertz (MHz) and a 50-MHz system bus interface. The FEIP has 8 megabytes (MB) of dynamic random access memory (DRAM). The FEIP microcode image is contained in the microcode ROM (U37). (See Figure 6-1.) The FEIP is interoperable with the Catalyst 5000 100BASE-T switch.

This section provides information about hardware requirements for the FEIP. Each FEIP is a fixed configuration; therefore, individual port adapters are not available as spare parts and are not field-replaceable or removable. The entire FEIP assembly is treated as a field-replaceable unit (FRU). Do not attempt to remove an FEIP port adapter and replace it with another.
The 100BASE-TX and 100BASE-FX interfaces support half- and full-duplex modes. Further, do not attempt to install or operate a mix of 100BASE-TX and 100BASE-FX interfaces on the same FEIP.
![]() | Caution Before you attach an MII transceiver to an MII receptacle on your FEIP, ensure that your MII transceiver responds to physical sublayer (PHY) address 0 per section 22.2.4.4. "PHY Address" of the IEEE 802.3u specification; otherwise, interface problems might result. Confirm that this capability is available on your MII transceiver with the transceiver's vendor or in the transceiver's documentation. If a selection for "Isolation Mode" is available, we recommend you use this setting (if no mention is made of "PHY addressing"). |
The FEIP configured with 100BASE-TX or 100BASE-FX interfaces (on port adapters) provides up to two 100-Mbps, Fast Ethernet (FE) interfaces. Each FE interface has an RJ-45 connector to attach to Category 5 unshielded twisted-pair (UTP) for 100BASE-TX, and an MII connector that permits connection through external transceivers to multimode fiber for 100BASE-FX, or to Category 3, 4, and 5 UTP or shielded twisted-pair (STP) for 100BASE-T4 physical media. Each FE port on the 100BASE-FX port adapter has an SC-type fiber-optic connector for 100BASE-FX, and an MII connector that permits connection through external transceivers to multimode fiber for 100BASE-FX, or to Category 3, 4, and 5 UTP or shielded twisted-pair (STP) for 100BASE-T4 physical media.
The 100BASE-TX and 100BASE-FX interfaces are shown in Figure 6-2 and Figure 6-3.


Each FE interface on an FEIP can be configured at 100 Mbps, half duplex or full duplex, for a maximum aggregate bandwidth of 200 Mbps.
![]() | Caution To prevent oversubscribing the FEIP, we recommend that you do not operate both FE interfaces on an FEIP in full-duplex mode. |
![]() | Caution To prevent system problems, do not simultaneously connect cables to the RJ-45 (or SC) and MII receptacles on a single FEIP port adapter. Each FE interface (100BASE-FX or 100BASE-TX) can have either an MII attachment or an RJ-45 (or SC) attachment, but not both. The MII and RJ-45 (or SC) receptacles represent two physical connection options for one FE interface. |
(An equal sign [=] indicates the entire FEIP2 assembly is available as a spare part.)
![]() | Caution To prevent system problems, do not exchange FEIP2 interfaces with FEIP interfaces. |
This section provides information about hardware requirements for the FEIP2. Each FEIP2 is a fixed configuration; therefore, individual port adapters are not available as spare parts and are not field-replaceable or removable. The entire FEIPs assembly is treated as a field-replaceable unit (FRU). Do not attempt to remove an FEIP2 port adapter and replace it with another.
The 100BASE-TX and 100BASE-FX interfaces support half- and full-duplex modes. Further, do not attempt to install or operate a mix of 100BASE-TX and 100BASE-FX interfaces on the same FEIP2.
In Cisco 7000 series routers, proper operation of the FEIP2 requires that the 7000 Series Route Switch Processor (RSP7000) and 7000 Series Chassis Interface (RSP7000CI) be installed. Further, we recommend that your Route Switch Processor (RSP) or RSP7000 has at least 24 MB of DRAM, or more.
![]() | Caution Before you attach an MII transceiver to an MII receptacle on your FEIP2, ensure that your MII transceiver responds to physical sublayer (PHY) address 0 per section 22.2.4.4. "PHY Address" of the IEEE 802.3u specification; otherwise, interface problems might result. Confirm that this capability is available on your MII transceiver with the transceiver's vendor or in the transceiver's documentation. If a selection for "Isolation Mode" is available, we recommend you use this setting (if no mention is made of "PHY addressing"). |
Each 100BASE-TX interface on the FEIP2-2TX (see Figure 6-4) has an RJ-45 connector to attach to Category 5 unshielded twisted-pair (UTP) for 100BASE-TX, and an MII connector that permits connection through external transceivers to multimode fiber for 100BASE-FX, or to Category 3, 4, and 5 UTP or shielded twisted-pair (STP) for 100BASE-T4 physical media.
Each 100BASE-FX interface on the FEIP2-2FX (see Figure 6-5) has an SC-type fiber-optic connector for 100BASE-FX, and an MII connector that permits connection through external transceivers to multimode fiber for 100BASE-FX, or to Category 3, 4, and 5 UTP or shielded twisted-pair (STP) for 100BASE-T4 physical media.
Each FE interface on an FEIP2 can be configured at 100 Mbps, half duplex, for a maximum aggregate bandwidth of 200 Mbps per pair. Each FE interface on an FEIP2 can also be configured at 200 Mbps, full duplex, for a maximum aggregate bandwidth of 400 Mbps per pair. Further, one FE interface can be configured at 100 Mbps, half duplex, while the other FE interface can be configured at 200 Mbps, full duplex, for a maximum aggregate bandwidth of 300 Mbps.

![]() | Caution To prevent system problems, do not simultaneously connect cables to the RJ-45 (or SC) and MII receptacles on a single FEIP2 FE interface. Each FE interface (100BASE-FX or 100BASE-TX) can have either an MII attachment or an RJ-45 (or SC) attachment, but not both. The MII and RJ-45 (or SC) receptacles represent two physical connection options for one FE interface. |

This section provides information on FEIP and FEIP2 interface cables, their pinouts and specifications, and instructions for attaching Fast Ethernet interface cables to the FEIP and FEIP2.
The two interface receptacles on the FEIP port adapter are a single MII, 40-pin, D-shell type, and a single RJ-45. You can use either one or the other. Only one receptacle can be used at one time. Each connection supports IEEE 802.3u interfaces compliant with the 100BASE-FX and 100BASE-TX standards.
The RJ-45 connection does not require an external transceiver; the MII connection requires an external physical sublayer (PHY) and an external transceiver. Figure 6-6 shows the RJ-45 cable connectors. RJ-45 cables are not available from Cisco Systems; they are available from commercial cable vendors. Table 6-1 lists the pinouts and signals for the RJ-45 connectors.

![]() | Warning The ports labeled "Ethernet," "10BASE-T," "Token Ring," "Console," and "AUX" are safety extra-low voltage (SELV) circuits. SELV circuits should only be connected to other SELV circuits. Because the BRI circuits are treated like telephone-network voltage, avoid connecting the SELV circuit to the telephone network voltage (TNV) circuits. |
| Pin | Description |
|---|---|
| 1 | Receive Data + (RxD+) |
| 2 | RxD- |
| 3 | Transmit Data + (TxD+) |
| 4 and 5 | Not used |
| 6 | TxD- |
| 7 and 8 | Not used |
For RJ-45 connections, two types of cabling are available: straight-through and crossover. Depending on your RJ-45 interface cabling requirements, use the pinouts illustrated in Figure 6-7 and Figure 6-8.


Figure 6-9 shows the duplex SC connector (one required for both transmit and receive), and Figure 6-10 shows the simplex SC connector (two required, one each for transmit and receive) used for 100BASE-FX optical-fiber connections. These multimode optical-fiber cables are commercially available; they are not available from Cisco Systems.


Depending on the type of media you use between the MII connection on the port adapter and your switch or hub, the network side of your 100BASE-T transceiver should be appropriately equipped: with SC-type or ST-type connectors (for optical fiber), BNC connectors, and so forth. Figure 6-11 shows the pin orientation of the female MII receptacle. Table 6-2 lists the MII receptacle's pinout and signals. MII cables are available commercially; they are not available from Cisco Systems.
The MII receptacle uses 2-56 screw-type locks, called jackscrews (shown in Figure 6-11), to secure the cable or transceiver to the MII port. MII cables and transceivers have knurled thumbscrews (screws you can tighten with your fingers) that you fasten to the jackscrews on the FEIP MII connector. Use the jackscrews to provide strain relief for your MII cable. (The RJ-45 modular plug has strain relief functionality incorporated into the design of its standard plastic connector.)

| Pin1 | In | Out | In/Out | Description |
|---|---|---|---|---|
| 14-17 | - | Yes | - | Transmit Data (TxD) |
| 12 | Yes | - | - | Transmit Clock (Tx_CLK)1 |
| 11 | - | Yes | - | Transmit Error (Tx_ER) |
| 13 | - | Yes | - | Transmit Enable (Tx_EN) |
| 3 | - | Yes | - | MII Data Clock (MDC) |
| 4-7 | Yes | - | - | Receive Data (RxD) |
| 9 | Yes | - | - | Receive Clock (Rx_CLK) |
| 10 | Yes | - | - | Receive Error (Rx_ER) |
| 8 | Yes | - | - | Receive Data Valid (Rx_DV) |
| 18 | Yes | - | - | Collision (COL) |
| 19 | Yes | - | - | Carrier Sense (CRS) |
| 2 | - | - | Yes | MII Data Input/Output (MDIO) |
| 22-39 | - | - | - | Common (ground) |
| 1, 20, 21, 40 | - | - | - | +5.0 volts (V) |
Table 6-3 lists the cabling specifications for 100-Mbps transmission over UTP, STP, and fiber-optic cables. Table 6-4 lists IEEE 802.3u physical characteristics for 100BASE-FX and 100BASE-TX.
| Parameter | RJ-45 | MII | SC-Type |
|---|---|---|---|
| Cable specification | Category 51 UTP2, 22 to 24 AWG3 | Category 3, 4, or 5, 150-ohm UTP or STP, or multimode optical fiber | 62.5/125 multimode optical fiber |
| Maximum cable length | - | 1.64 ft (0.5 m) (MII-to-MII cable4) | - |
| Maximum segment length | 328 ft (100 m) for 100BASE-TX | 3.28 ft (1 m)5 or 1,312 ft (400 m) for 100BASE-FX | 328 ft (100 m) |
| Maximum network length | 656 ft (200 m)5 (with 1 repeater) | - | 656 ft (200 m)5 (with 1 repeater) |
| Parameter | 100BASE-FX | 100BASE-TX |
|---|---|---|
| Data rate (Mbps) | 100 | 100 |
| Signaling method | Baseband | Baseband |
| Maximum segment length (meters) | 328 ft (100 m) between repeaters | 328 ft (100 m) between DTE1 and repeaters |
| Media | SC-type: dual simplex or single duplex for Rx and Tx | RJ-45MII |
| Topology | Star/Hub | Star/Hub |
On a single FE interface (on the FEIP and FEIP2), you can use either the RJ-45 (or SC for 100BASE-FX) connection or the MII connection. If you have two FE interfaces on your FEIP (or FEIP2), you can use the RJ-45 (or SC for 100BASE-FX) connection on one port adapter and the MII connection on the other port adapter.
If you have MII connections, attach an MII cable directly to the MII port, or attach a 100BASE-T transceiver, with the media appropriate to your application. (See Figure 6-12 for 100BASE-TX or Figure 6-13 for 100BASE-FX.)
![]() | Caution Before you attach an MII transceiver to an MII receptacle on your FEIP or FEIP2, ensure that your MII transceiver responds to physical sublayer (PHY) address 0 per section 22.2.4.4. "PHY Address" of the IEEE 802.3u specification; otherwise, interface problems might result. Confirm that this capability is available on your MII transceiver with the transceiver's vendor or in the transceiver's documentation. If a selection for "Isolation Mode" is available, we recommend you use this setting (if no mention is made of "PHY addressing"). |
If you have RJ-45 connections, attach the Category 5 UTP cable directly to the RJ-45 port on the FE interface. (See Figure 6-12 for 100BASE-TX or Figure 6-13 for 100BASE-FX.) The FE interface is an end station device and not a repeater. You must connect the FE interface to a repeater or hub.
If you have SC connections (100BASE-FX), attach the cable directly to the SC port on the 100BASE-FX interface. (See Figure 6-13.) Use either one duplex SC connector, or two simplex SC connectors, and observe the correct relationship between the receive (RX) and transmit (TX) ports on the 100BASE-FX interface and your repeater.


For 100BASE-TX connections, we strongly recommend you attach a ferrite bead (included) to the cable to reduce the effects of radiated EMI. Attach the ferrite bead around the RJ-45 cable (at either end), as shown in Figure 6-14.
![]() | Caution The ferrite bead prevents electromagnetic interference (EMI) from affecting the system and is a required component for proper system operation. |

Attach the network end of your RJ-45 (or SC) or MII cable to your 100BASE-T transceiver, switch, hub, repeater, DTE, or other external 100BASE-TX or 10BASE-FX equipment.
The FEIP and FEIP2 each have four status LEDs on their faceplates that indicate status on that port. (See Figure 6-15.)

Following are the functions of the FEIP and FEIP2 LEDs:
After you connect the cables, observe the LED states and the console display as the router initializes. When the system has reinitializes all interfaces, the enabled LED on the FEIP should go on.
The console screen will also display a message as the system discovers each interface during its reinitialization. After system initialization, the enabled LED goes on to indicate that the FEIP is enabled for operation.
The following conditions must be met before the FEIP or FEIP2 is enabled:
If any one of these conditions is not met, or if the initialization fails, the enabled LED does not go on.
Verify that the FEIP or FEIP2 is connected correctly as follows:
Step 1 While the system reinitializes each interface, observe the console display messages and verify that the system discovers the FEIP. The system should recognize the FEIP interfaces but should leave them configured as down.
Step 2 When the reinitialization is complete, verify that the enabled LED on each FEIP port adapter is on and remains on. If the LED does stay on, proceed to Step 5. If the enabled LED does not stay on, proceed to the next step.
Step 3 If an enabled LED fails to go on, suspect that the FEIP board connector is not fully seated in the backplane. Loosen the captive installation screws, then firmly push the top ejector down while pushing the bottom ejector up until both are parallel to the FEIP faceplate. Tighten the captive installation screws. After the system reinitializes the interfaces, the enabled LED on the FEIP should go on. If the enabled LED goes on, proceed to Step 5. If the enabled LED does not go on, proceed to the next step.
Step 4 If an enabled LED still fails to go on, remove the FEIP and try installing it in another available interface processor slot.
Step 5 Use the show interfaces or show controllers cbus command to verify the status of the FEIP interfaces. (If the interfaces are not configured, you must configure them using the procedures in the section "Configuring the FEIP.")
![]() | Caution To prevent system problems, do not exchange FE interfaces between the FEIP and FEIP2. |
If you experience other problems that you are unable to solve, contact a service representative for assistance.
If you want to change the configuration of an existing interface, you must enter configuration mode to change its configuration. If you replaced an FEIP or FEIP2 that was previously configured, the system will recognize the new interfaces and bring each of them up in their existing configuration.
After you verify that the new Fast Ethernet interfaces are installed correctly (the enabled LED goes on), use the privileged-level configure command to configure the new interfaces. Be prepared with the information you will need, such as the following:
For a summary of the configuration options available and for instructions for configuring the interfaces, refer to the appropriate software configuration publications listed in the section "If You Need More Information" in the chapter "Using Interface Processors."
Configuring the FEIP first requires privileged-level access to the EXEC command interpreter. (Refer to the section "Using the EXEC Command Interpreter" in the chapter "Using Interface Processors.") Also, privileged-level access usually requires a password. (Contact your system administrator, if necessary, to obtain privileged-level access.)
In the router, physical port addresses specify the actual physical location of each interface port on the router interface processor end. For the FEIP, the address is composed of a three-part number in the format slot/port-adapter/port number, as follows:
On the FEIP and FEIP2, individual FE interface port numbers are always 0; however, two FE interfaces on an FEIP are numbered 0 and 1 because up to two FE interfaces per card are supported. The MII and RJ-45 (or SC) ports each have the same port number because only one of them can be used at one time.
Interface ports maintain the same address regardless of whether other interface processors are installed or removed. However, when you move an interface processor to a different interface processor slot, the first number in the address changes to reflect the new interface processor slot number. For example, on a one-port FEIP in interface processor slot 3, the address of the Fast Ethernet port is 3/0/0: interface processor slot 3, port adapter slot 0, and interface 0. If you remove the FEIP from interface processor slot 3 and install it in slot 2, the address of the Fast Ethernet port becomes 2/0/0. (The preceding example applies to FEIP2; however, the address of both FE interfaces would change.)
You can also identify interface ports by physically checking the slot/port location on the rear of the router or by using software commands to display information about a specific interface or all interfaces in the router.
This section provides descriptions and examples of the basic commands required to configure the Fast Ethernet interfaces. Depending on the requirements for your system configuration and the protocols you plan to route on the interface, you might also need to enter other configuration subcommands. (For additional descriptions of configuration subcommands and the configuration options available for Fast Ethernet interfaces, refer to the publications listed in the section "If You Need More Information" in the chapter "Using Interface Processors.") Descriptions are limited to fields that are relevant for establishing and verifying a basic configuration. After configuring the new FEIP interface, use show commands to display the status of the new interface or all interfaces, or to verify changes you have made.
Each FE interface on an FEIP can be configured at 100 Mbps, half duplex or full duplex, for a maximum aggregate bandwidth of 200 Mbps.
![]() | Caution To prevent oversubscribing the FEIP, we recommend that you do not operate both FE interfaces on an FEIP in full-duplex mode. |
Each FE interface on an FEIP2 can be configured at 100 Mbps, half duplex, for a maximum aggregate bandwidth of 200 Mbps per pair. Each FE interface on an FEIP2 can also be configured at 200 Mbps, full duplex, for a maximum aggregate bandwidth of 400 Mbps per pair. Further, one FE interface can be configured at 100 Mbps, half duplex, while the other FE interface can be configured at 200 Mbps, full duplex, for a maximum aggregate bandwidth of 300 Mbps.
The 100BASE-TX and 100BASE-FX interfaces support half- and full-duplex modes; half-duplex operation is the default. To change the interfaces to full-duplex operation, use the following series of commands:
Router#configure terminalEnter configuration commands, one per line. End with CNTL/Z. Router(config)# Router(config)#interface fastethernet 0/0/0Router(config-if)#full-duplexCtrl-zRouter#
Using the show interfaces fastethernet 0/0/0 command, you can see that the interface is now configured for full-duplex operation, as follows:
Router# sh int fa 0/0/0
FastEthernet0/0/0 is administratively down, line protocol is down
(additional displayed text omitted from this example)
Encapsulation ARPA, loopback not set, keepalive not set, fdx, 100BaseFX
(additional displayed text omitted from this example)
To return the interface to half-duplex operation, use the no full-duplex configuration command as follows:
Router#config tEnter configuration commands, one per line. End with CNTL/Z. Router(config)#int fa 0/0/0Router(config-if)#no fullCtrl-zRouter#
Using the show interfaces fastethernet 0/0/0 command, you can see that the interface is now configured for half-duplex operation, as follows:
Router# sh int fa 0/0/0
FastEthernet0/0/0 is administratively down, line protocol is down
(additional displayed text omitted from this example)
Encapsulation ARPA, loopback not set, keepalive not set, hdx, 100BaseFX
(additional displayed text omitted from this example)
The RJ-45 connection is the default for 100BASE-TX (or SC for 100BASE-FX). To change to an MII connection and then verify it, use the following series of commands, including the media-type configuration command:
Router#config tEnter configuration commands, one per line. End with CNTL/Z. Router(config)#int fa 0/0/0Router(config-if)#media-type miiCtrl-zRouter# Router#sh int fa 0/0/0FastEthernet0/0/0 is administratively up, line protocol is up (additional displayed text omitted from this example) Encapsulation ARPA, loopback not set, keepalive not set, hdx, MII (additional displayed text omitted from this example)
Use the media-type 100 configuration command to return the interface to its default state for RJ-45 or SC (fiber-optic) connections.
The following procedure describes how to use the show commands to verify that the new interfaces are configured correctly:
Step 1 Use the show version command to display the system hardware configuration. Ensure that the list includes the new Fast Ethernet interfaces.
Step 2 Display all of the current interface processors and their interfaces with the show controllers cbus command. Verify that the new FEIP appears in the correct interface processor slot.
Step 3 Specify one of the new FEIP interfaces with the show interface fastethernet slot/port adapter/port command and verify that the first line of the display specifies the interface with the correct slot number. Also verify that the interface and line protocol are in the correct state: up or down.
Step 4 Display the protocols configured for the entire system and specific interfaces with the command show protocols. If necessary, return to the configuration mode to add or remove protocol routing on the system or specific interfaces.
Step 5 Display the entire system configuration file with the show configuration command. Verify that the configuration is accurate for the system and each interface.
If the interface is down and you configured it as up, or if the displays indicate that the hardware is not functioning properly, ensure that the network interface is properly connected and terminated. If you still have problems bringing the interface up, contact a service representative for assistance.
Router# show int
(additional displayed text omitted from this example)
FastEthernet0/0/0 is up, line protocol is up
Hardware is cxBus FastEthernet, address is 0000.0c03.4a3b (bia 0000.0c03.4a3b)
(additional displayed text omitted from this example)
You can also use arguments such as the interface type (fastethernet, and so forth) and the port address (slot/port-adapter/port) to display information about a specific interface only.
The following example of the show interfaces fastethernet command shows information specific to the FEIP port in interface processor slot 0:
Router#show interfaces fastethernet 0/0/0FastEthernet0/0/0 is administratively down, line protocol is down Hardware is cxBus FastEthernet, address is 0000.0c35.dc16 (bia 0000.0c35.dc16) Internet address is 1.1.0.64 255.255.0.0 MTU 1500 bytes, BW 100000 Kbit, DLY 100 usec, rely 255/255, load 1/255 Encapsulation ARPA, loopback not set, keepalive not set, hdx, MIIARP type: ARPA, ARP Timeout 4:00:00 Last input never, output 2:03:52, output hang never Last clearing of "show interface" counters never Output queue 0/40, 0 drops; input queue 0/75, 1 drops 5 minute input rate 0 bits/sec, 0 packets/sec 5 minute output rate 0 bits/sec, 0 packets/sec 0 packets input, 0 bytes, 0 no buffer Received 0 broadcasts, 0 runts, 0 giants 0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored, 0 abort 0 watchdog, 0 multicast 0 input packets with dribble condition detected 5 packets output, 805 bytes, 0 underruns 0 output errors, 0 collisions, 4 interface resets, 0 restarts 0 babbles, 0 late collision, 0 deferred 0 lost carrier, 0 no carrier 0 output buffer failures, 0 output buffers swapped out
The show version command displays the configuration of the system hardware (the number of each interface processor type installed), the software version, the names and sources of configuration files, and the boot images.
The following example shows the display output of the show version command used with a Cisco 7500 series system:
Router# show version
Cisco Internetwork Operating System Software
IOS (tm) GS Software (RSP-JV-M), Released Version 11.1(10)CA [biff 135]
Copyright (c) 1986-1997 by cisco Systems, Inc.
Compiled Sat 10-May-97 06:02 by mpo
Image text-base: 0x600108A0, data-base: 0x60982000
ROM: System Bootstrap, Version 11.1(2) [biff 2], RELEASE SOFTWARE (fc1)
ROM: GS Bootstrap Software (RSP-BOOT-M), Version 10.3(8), RELEASE SOFTWARE (fc2)
Router uptime is 23 minutes
System restarted by reload
System image file is "biff/rsp-jv-mz", booted via tftp from 223.255.254.254
cisco RSP2 (R4600) processor with 32768K bytes of memory.
R4700 processor, Implementation 33, Revision 1.0
Last reset from power-on
G.703/E1 software, Version 1.0.
SuperLAT software copyright 1990 by Meridian Technology Corp).
Bridging software.
X.25 software, Version 2.0, NET2, BFE and GOSIP compliant.
TN3270 Emulation software (copyright 1994 by TGV Inc).
Chassis Interface.
(additional displayed text omitted from this example)
1 FEIP2 controller (2 FastEthernet).
2 FastEthernet/IEEE 802.3 interfaces.
(additional displayed text omitted from this example)
123K bytes of non-volatile configuration memory.
8192K bytes of Flash PCMCIA card at slot 0 (Sector size 128K).
8192K bytes of Flash internal SIMM (Sector size 256K).
No slave installed in slot 7.
Configuration register is 0x0
The show controllers cbus command displays the internal status of each interface processor, including the slot location, the card hardware version, and the currently running microcode version. It also lists each interface (port) on each interface processor including the logical interface number, interface type, physical (slot/port adapter/port) address, and hardware (station address) of each interface.
The following example shows an FEIP2 installed in interface processor slot 0:
Router# show controllers cbus
MEMD at 40000000, 2097152 bytes (unused 8256, recarves 1, lost 0)
RawQ 48000100, ReturnQ 48000108, EventQ 48000110
BufhdrQ 48000128 (2357 items), LovltrQ 48000148 (6 items, 1632 bytes)
IpcbufQ 48000158 (16 items, 4096 bytes)
IpcbufQ_classic 48000150 (8 items, 4096 bytes)
3570 buffer headers (48002000 - 4800FF10)
pool0: 11 buffers, 256 bytes, queue 48000130
pool1: 1168 buffers, 1536 bytes, queue 48000138
pool2: 4 buffers, 1568 bytes, queue 48000140
(additional displayed text omitted from this example)
slot0: FEIP2, hw 2.4, sw 21.40, ccb 5800FF40, cmdq 48000090, vps 8192
software loaded from system
IOS (tm) VIP Software (SVIP-DW-M), Released Version 11.1(10)CA [biff 138]
ROM Monitor version 17.0
FastEthernet0/0/0, addr 0003.0b33.f540 (bia 0003.0b33.f540)
gfreeq 48000138, lfreeq 480001C0 (1536 bytes), throttled 0
rxlo 4, rxhi 438, rxcurr 0, maxrxcurr 2
txq 48001A00, txacc 48001A02 (value 259), txlimit 259
FastEthernet0/1/0, addr 0003.0b33.f548 (bia 0003.0b33.f548)
gfreeq 48000138, lfreeq 480001C8 (1536 bytes), throttled 0
rxlo 4, rxhi 438, rxcurr 0, maxrxcurr 0
txq 48001A08, txacc 48001A0A (value 0), txlimit 259
(additional displayed text omitted from this example)
For complete command descriptions and instructions, refer to the software configuration publications listed in the section "If You Need More Information" in the chapter "Using Interface Processors."
This completes the configuration procedure for new Fast Ethernet interfaces.
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