NPE-175 and NPE-225 Overview

This chapter describes the network processing engine (NPE) models NPE-175 and NPE-225 and contains the following sections:

Supported Platforms

Table 2-1 provides information about the platforms supported by the NPE-175 and NPE-225.

Table 2-1: NPE-175 and NPE-225 Supported Platforms

NPE Platform

NPE-175

Cisco 7200 routers, Cisco 7200 VXR routers, Cisco uBR7246, Cisco uBR7246 VXR universal broadband router, and Cisco uBR7223 universal broadband router

NPE-225

Cisco 7200 routers, Cisco 7200 VXR routers, Cisco uBR7246 VXR universal broadband router, Cisco uBR7246 and Cisco uBR7223 universal broadband routers

NPE	Platform
NPE-175	Cisco 7200 routers, Cisco 7200 VXR routers, Cisco uBR7246, Cisco uBR7246 VXR universal broadband router, and Cisco uBR7223 universal broadband router
NPE-225	Cisco 7200 routers, Cisco 7200 VXR routers, Cisco uBR7246 VXR universal broadband router, Cisco uBR7246 and Cisco uBR7223 universal broadband routers

NPE-175 and NPE-225 Description

The information about the network processing engine components and the system management functions are in this section. The network processing engine maintains and executes the system management functions for the Cisco 7200 series and Cisco uBR7200 series routers. The NPE also shares the system memory and environmental monitoring functions with the I/O controller.

Components

Figure 2-1: NPE-175

Figure 2-2: NPE-225

The NPE-175 and NPE-225 consist of the following components:

Reduced instruction set computing (RISC) microprocessor
- The NPE-175 has an RM5270 microprocessor that operates at an internal clock speed of 200 MHz.
- The NPE-225 has an RM5271 microprocessor that operates at an internal clock speed of 262 MHz.
System controller

: The system controller provides hardware logic to interconnect the processor, DRAM, and the PCI-based system backplane bus. The NPE-175 and NPE-225 have one system controller that provides processor access to the two midplane and single I/O controller peripheral component interconnect (PCI) buses. The system controller also allows port adapters on either of the two midplane PCI buses access to SDRAM.

Upgradable memory modules

: The NPE-175 and NPE-225 use SDRAM for providing code, data, and packet storage.

Cache memory

: The NPE-175 and NPE-225 have unified cache SRAM that functions as the secondary cache for the microprocessor. (The primary cache is within the microprocessor.)

Two environmental sensors for monitoring the cooling air as it leaves the chassis
Boot ROM for storing sufficient code for booting the Cisco IOS software; the NPE-175 and NPE-225 have boot ROM

Note Neither the NPE-175 nor the NPE-225 has packet SRAM.

System Management Functions

The network processing engines and network services engine perform the following system management functions:

Sending and receiving routing protocol updates

Managing tables, caches, and buffers

Monitoring interface and environmental status

Providing Simple Network Management Protocol (SNMP) management through the console and Telnet interface
Accounting for and switching of data traffic
Booting and reloading images
Managing port adapters (including recognition and initialization during online insertion and removal)

NPE-175 and NPE-225 Memory Information

To determine the memory configuration of your NPE, use the show version command.

The following example shows an NPE-225 installed in a Cisco 7206VXR router:

router(boot)# show version
Cisco Internetwork Operating System Software 
IOS (tm) 7200 Software (C7200-BOOT-M), Released Version 12.0(19990124:222541) [biff-nightly 115]
Copyright (c) 1986-1999 by cisco Systems, Inc.
Compiled Mon 15-Feb-99 21:50 by biff
Image text-base:0x600088F8, data-base:0x6064C000
 
  (display text omitted)
 
cisco 7206VXR (NPE225) processor with 57344K/8192K bytes of memory.
R527x CPU at 262Mhz, Implementation 40, Rev 10.0, 2048KB L2 Cache
6 slot VXR midplane, Version 2.0
 
  (display text omitted)

Table 2-2 provides memory specifications, and Table 2-3 provides memory configurations for the NPE-175 and NPE-225.

Terms and Acronyms

DIMM—dual in-line memory module
DRAM—dynamic random-access memory
OTP—one time programmable
RAM—random-access memory
RISC—reduced instruction set computing
ROM—read-only memory
SIMM—single in-line memory module
SDRAM—synchronous dynamic random-access memory
SDRAM-fixed—SDRAM of a fixed size or quantity; can be replaced, but not upgraded
SRAM—static random-access memory
Cache—Memory with fast access and small capacity used to temporarily store recently accessed data; found either incorporated into the processor or near it.
Primary, secondary, tertiary cache—Hierarchical cache memory storage based on the proximity of the cache to the core of the processor. Primary cache is closest to the processor core and has the fastest access. Secondary cache has slower access than primary cache, but faster access than tertiary cache.
Instruction and data cache— Instructions to the processor, and data on which the instructions work.
Unified cache— Instruction cache and data cache are combined. For example, a processor may have primary cache with separate instruction and data cache memory, but unified secondary cache.
Integrated cache—Cache that is built into the processor; sometimes referred to as internal cache. Cache memory physically located outside the processor is not integrated, and is sometimes referred to as external cache.

Table 2-2: NPE-175 and NPE-225 Memory Specifications

Memory Type Size Quantity Description Location

SDRAM

64 or 128 MB

1 configurable bank with 1 SDRAM slot

DIMM

U15

Boot ROM

512 KB

1

OTP ROM for the ROM monitor program

U1

Primary cache

16 KB (instruction),
16 KB (data)

—

RM5270 processor primary internal cache

U4

32 KB (instruction),
32 KB (data)

—

RM5271 processor primary internal cache

U4

Secondary cache

2 MB

4 x 256 x 18 bits = 64 bit plus 4 parity bits

RM527x processor, unified external cache

U5, U6, U7, U8¹

¹Located on the Processor Engine board.

Memory Type	Size	Quantity	Description	Location
SDRAM	64 or 128 MB	1 configurable bank with 1 SDRAM slot	DIMM	U15
Boot ROM	512 KB	1	OTP ROM for the ROM monitor program	U1
Primary cache	16 KB (instruction), 16 KB (data)	—	RM5270 processor primary internal cache	U4
	32 KB (instruction), 32 KB (data)	—	RM5271 processor primary internal cache	U4
Secondary cache	2 MB	4 x 256 x 18 bits = 64 bit plus 4 parity bits	RM527x processor, unified external cache	U5, U6, U7, U8¹

Table 2-3: NPE-175 and NPE-225 SDRAM DIMM Configurations—Configurable Memory Only

Total SDRAM SDRAM Bank Quantity Product Number

64 MB

U15

1 64-MB DIMM

MEM-SD-NPE-64MB

128 MB

U15

1 128-MB DIMM

MEM-SD-NPE-128MB

Total SDRAM	SDRAM Bank	Quantity	Product Number
64 MB	U15	1 64-MB DIMM	MEM-SD-NPE-64MB
128 MB	U15	1 128-MB DIMM	MEM-SD-NPE-128MB

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