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Release Notes for Catalyst 8540 MSR and CSR Route Processor FPGA Image Release 4.7

Release Notes for Catalyst 8540 MSR and CSR Route Processor FPGA Image Release 4.7

February 8, 2000

Catalyst 8540 MSR and CSR route processor (product numbers C8545MSR-MRP and C8541CSR-RP) FPGA image name fi-c8540-rp.A.4-7.bin

Text Product Number OL-0231-03 B0

This document describes the features and caveats for Cisco field-programmable gate array (FPGA) functional image, fi-c8540-rp.A.4-7.bin, for the route processors used with the Catalyst 8540 MSR and CSR.

This version of the route processor FPGA image fixes a problem that occurs when the switch attempts to reprogram the ROMMON. This problem is listed in the section "Caveat Symptoms and Workarounds" later in this release note.

Contents

This release note includes the following sections:

Introduction

The Catalyst 8540 MSR and CSR provide switched ATM connections to individual workstations, servers, LAN segments, or other ATM switches and routers using fiber-optic, unshielded twisted-pair (UTP), and coaxial cable.

Slots 4 and 8 of the Catalyst 8540 MSR and CSR chassis are occupied by the dual, field-replaceable route processors, which perform central processing functions and provide redundancy. The route processors can also accommodate the network clock module, which features a stratum 3 oscillator and two building integrated timing supply (BITS) ports.

Determining Your Route Processor FPGA Image Release

This section describes the process you use to determine the existing FPGA functional image version installed on your route processor.

To display the functional image version in a route processor, use the following command in privileged EXEC mode:

Command

Purpose

 show functional-image-info {slot number | subslot slot/subslot} 


 Displays the functional image information.

Example

The following example shows the FPGA functional image information for the route processor in slot 4:

Switch# show functional-image-info slot 4
 
Details for cpu Image on slot: 4
 
Functional Version of the FPGA Image: 4.7
 #Jtag-Distribution-Format-B
 #HardwareRequired: 100(3.0-9,4.0-9,5.0-9)
 #FunctionalVersion: 4.7
 #Sections: 1
 #Section1Format: MOTOROLA_EXORMAX
 
  Copyright (c) 1996-99 by cisco Systems, Inc.
  All rights reserved.
  generated by:       holliday
  on:                 Fri Feb 12 20:16:20 PST 1999
  using:              /cougar/bin/jtag_script Version 1.09
  config file:        cpu.jcf
 
  Chain description:
  Part type Bits Config file
  10k50     10   /cougar/custom/cpu/cidrFpga2/max/cidr_fpga.ttf
  xcs4062   3    /cougar/custom/cpu/cubiFpga2/xil/cubi.bit
  xcs4062   3    /cougar/custom/cpu/cubiFpga2/xil/cubi.bit
  generic   2
  XC4005    3    /cougar/custom/common/jtcfg/xil/jtcfg_r.bit
  Number devices             = 5
  Number of instruction bits = 21
 
  FPGA config file information:
  Bitgen date/time  Sum   File
  99/02/12 20:13:05 65332 /cougar/custom/cpu/cidrFpga2/max/cidr_fpga.ttf
  1998/12/11 12:22:45 53110 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit
  1998/12/11 12:22:45 53110 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit
  98/06/11 16:56:44 49904 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit
 
  #End-Of-Header
Note    In the previous show function-image-info command output, the functional version appeared as 4.7 corresponding to the 4-7 string in the file name "fi-c8540-rp.A.4-7.bin."

Updating to a New Release

For detailed FPGA image upgrade instructions, see the "Maintaining Functional Images" section in the "Managing Configuration Files, System Images, and Functional Images" chapter of the ATM Switch Router Software Configuration Guide.

Caution FPGA image download cannot be reverted back once the download is started. Do not interrupt the download procedure. Wait until it has finished before attempting any commands on the switch. Confirm that the download is done in binary mode and check file sizes before and after download. A failure during reprogramming can result in the card being unusable.

Caveats

This section contains a listing of the caveats for this route processor FPGA functional image.

Use Table 1 to determine the status of a particular caveat and its relevancy to your FPGA functional image release. These caveats are described in detail in the following section, "Caveat Symptoms and Workarounds." In the table, "Y" indicates a fixed caveat, and "N" indicates an open caveat.


Table 1: Route Processor FPGA Image Release Caveats and Caveats Corrected Reference
DDTS Number FPGA Release 4.7 FPGA Release 4.6 FPGA Release 4.5

CSCdp44579

Y

N

N

CSCdp05103

Y

N

N

CSCdm87966

-

Y

N

CSCdk67290

-

-

Y

Caveat Symptoms and Workarounds

This section describes the resolved caveats for this route processor FPGA functional image:

  Symptom: When running IOS, the route processor sometimes prints a message similar to the following:
     *Sep 25 23:38:04.596: %CPUPORTMONITOR-2-PIF_RESET_MSG: 
 **** PIF Reset detected - System will be reloaded in 30 seconds ****
  When this error occurs the route processor no longer sends or receives traffic. The switch fabric might still pass traffic.
  Workaround: Upgrade the route processor FPGA image to fi-c8540-rp.A.4-7 or later.
  Symptom: When attempting to reprogram the ROMMON, the switch hangs after displaying the following message:
         Resetting in 3 seconds
  Workaround: Upgrade the route processor FPGA image to fi-c8540-rp.A.4-7 or later.
  Symptom: When powering up and booting the switch router with two route processors or installing a second route processor in a working switch, the following message appears on the console port of the secondary route processor.
    SECONDARY CPU:    *** Failure - Can not sync to other CPUs sync ****
Sys Clock lock and sync failed.
  The secondary route processor fails to boot and the switch router is in a nonredundant mode.
  This is caused when the Catalyst 8540 MSR or CSR has two route processors and the secondary route processor has an FPGA image version of 4.5 or less.
  Workaround: Upgrade the route processor FPGA image to Version 4.6 or greater.
  Other temporary workarounds are to power cycle the switch router or OIR (online insertion and removal) the secondary route processor.
  Symptom: In a network running PNNI, flat as well as hierarchical, the following error message appears:
     %PNNI-4-BADPACKET: Invalid PTSP pkt: Fails Length Check 2 88
  This sometimes results in an incorrect PNNI database, causing nonconnectivity, and shows reachable nodes as being unreachable.
   Workaround: Upgrade the route processor FPGA image to fi-c8540-rp.A.4-5.

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Posted: Fri Aug 25 09:46:53 PDT 2000
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