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August 31, 1999
Catalyst 8540 MSR and CSR route processor (product number C8540 MSR RP) FPGA image name fi-c8540-rp.A.4-6
This document describes the features and caveats for Cisco field-programmable gate array (FPGA) functional image, fi-c8540-rp.A.4-6, for the route processors used with the Catalyst 8540 MSR and CSR.
This version of route processor FPGA image fixes a problem that occurs when powering up and booting the switch router and the secondary route processor fails to boot and the switch router remains in non-redundant mode. This problem is listed in the section "Caveats" later in this release note.
This release note includes the following sections:
The Catalyst 8540 MSR and CSR provide switched ATM connections to individual workstations, servers, LAN segments, or other ATM switches and routers using fiber-optic, unshielded twisted-pair (UTP), and coaxial cable.
Slots 4 and 8 of the Catalyst 8540 MSR and CSR chassis are occupied by the dual, field-replaceable route processors, which perform central processing functions and provide redundancy. The route processors can also accommodate the network clock module, which features a stratum 3 oscillator and two building integrated timing supply (BITS) ports.
This section describes the process you use to determine the existing FPGA functional image version installed on your route processor.
To display the functional image version in a route processor, use the following command in privileged EXEC mode:
| Command | Purpose |
|---|---|
show functional-image-info [slot number | subslot slot/subslot] | Displays the functional image information. |
The following example shows the FPGA functional image information for the route processor in slot 4:
Switch# show functional-image-info slot 4 Details for cpu Image on slot: 4
Functional Version of the FPGA Image: 4.6 #Jtag-Distribution-Format-B #HardwareRequired: 100(3.0-9,4.0-9,5.0-9) #FunctionalVersion: 4.6 #Sections: 1 #Section1Format: MOTOROLA_EXORMAX Copyright (c) 1996-99 by cisco Systems, Inc. All rights reserved. generated by: holliday on: Fri Feb 12 20:16:20 PST 1999 using: /cougar/bin/jtag_script Version 1.09 config file: cpu.jcf Chain description: Part type Bits Config file 10k50 10 /cougar/custom/cpu/cidrFpga2/max/cidr_fpga.ttf xcs4062 3 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit xcs4062 3 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit generic 2 XC4005 3 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit Number devices = 5 Number of instruction bits = 21 FPGA config file information: Bitgen date/time Sum File 99/02/12 20:13:05 65332 /cougar/custom/cpu/cidrFpga2/max/cidr_fpga.ttf 1998/12/11 12:22:45 53110 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit 1998/12/11 12:22:45 53110 /cougar/custom/cpu/cubiFpga2/xil/cubi.bit 98/06/11 16:56:44 49904 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit #End-Of-Header
For detailed FPGA image upgrade instructions, see the "Maintaining Functional Images" section in the "Managing Configuration Files, System Images, and Functional Images" chapter of the ATM Switch Router Software Configuration Guide.
 | Caution FPGA image download can not be reverted back once the download is started. Do not interrupt the download procedure. Wait until it has finished before attempting any commands on the switch. Confirm that the download is done in binary mode and check file sizes before and after download. A failure during reprogramming can result in the card being unusable. |
This section contains listings of the caveats for this route processor FPGA functional image.
Use Table 1 to determine if a particular caveat applies to your FPGA functional image release, or if a particular caveat was corrected in your FPGA or firmware image release. These caveats are described in detail in the following section "Resolved Caveats."
Table 1 lists the known caveats and corrected caveats for this route processor FPGA image.
| DDTS Number | FPGA Release 4.6 | FPGA Release 4.5 | ||
|---|---|---|---|---|
| Corrected | Caveat | Corrected | Caveat | |
CSCdm87966 | x |
|
| x |
CSCdk67290 | x |
| x |
|
This section describes the resolved caveats for this route processor FPGA functional image:
SECONDARY CPU: *** Failure - Can not sync to other CPUs sync **** Sys Clock lock and sync failed.
%PNNI-4-BADPACKET: Invalid PTSP pkt: Fails Length Check 2 88
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Posted: Fri Aug 25 09:55:32 PDT 2000
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