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June 14, 1999
Catalyst 8540 MSR feature card (product number C8546MSR-MSP-FCL) FPGA image name fi-c8540-fc.A.4-17
This document describes the features and caveats for Cisco field-programmable gate array (FPGA) functional image, fi-c8540-fc.A.4-17, for the feature cards used with the Catalyst 8540 MSR.
This version of feature card FPGA image fixes the per-VC transmit statistics counter problem listed in the section "Caveats" later in this release note.
This release note includes the following sections:
The Catalyst 8540 MSR provide switched ATM connections to individual workstations, servers, LAN segments, or other ATM switches and routers using fiber-optic, unshielded twisted-pair (UTP), and coaxial cable.
Slots 5, 6, and 7 of the Catalyst 8540 MSR chassis are occupied by either two or three switch processors, for a 20-Gbps non-EHSA or 20-Gbps Enhanced High System Availability (EHSA) switch fabric. The switch processors also accommodate the optional switch processor feature card. The switch feature card supports usage parameter control (UPC) and statistics.
This section describes the process you use to determine the existing FPGA functional image version installed on your feature card.
To display the functional image version in a feature card, use the following command in privileged EXEC mode:
| Command | Purpose |
|---|---|
show functional-image-info [slot number | subslot slot/subslot] | Displays the functional image information. |
The following example shows the FPGA functional image information for the feature card in slot 5:
Switch# show functional-image-info slot 5 Details for Switch Card Image on slot: 5 Functional Version of the FPGA Image: 1.4 #Jtag-Distribution-Format-B #HardwareRequired: 102(3.0-20,4.0-20,5.0-20,6.0-20,7.0-9,8.0-9) #FunctionalVersion: 1.4 #Sections: 2 #Section1Format: MOTOROLA_EXORMAX #Section2Format: XILINX_XSVF, length=385913 Copyright (c) 1996-99 by cisco Systems, Inc. All rights reserved. generated by: chl on: Sat Feb 27 14:38:20 PST 1999 using: /cougar/bin/jtag_script Version 1.10 config file: switch_msr.jcf Chain description: Part type Bits Config file xc4044 3 /cougar/custom/switch/decode_2/synopsys/decode_2_r.bit xc95108 8 /cougar/custom/switch/cpu_mux/epld/cpu_mux.jed xc95108 8 /cougar/custom/switch/cpu_mux/epld/cpu_mux.jed xc4005 3 /cougar/custom/switch/cid_mux2/xilinx/cid_mux2_r.bit xc4005 3 /cougar/custom/switch/ovc_mux2/xilinx/ovc_mux2_r.bit xc4005 3 /cougar/custom/switch/ovc_mux2/xilinx/ovc_mux2_r.bit xc4005 3 /cougar/custom/switch/cid_mux2/xilinx/cid_mux2_r.bit xc4036 3 /cougar/custom/switch/ext_log2/xilinx/ext_log2_r.bit generic 2 generic 2 generic 2 generic 2 generic 2 generic 3 generic 3 generic 2 generic 2 generic 2 generic 2 generic 2 generic 2 generic 3 generic 3 generic 2 generic 2 generic 2 generic 2 generic 2 generic 2 generic 2 generic 2 generic 2 XC4005 3 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit Number devices = 33 Number of instruction bits = 89 FPGA config file information: Bitgen date/time Sum File 1999/02/27 11:21:10 34696 /cougar/custom/switch/decode_2/synopsys/decode_2_r.b it 98/11/15 11:55:51 11860 /cougar/custom/switch/cpu_mux/epld/cpu_mux.jed 98/11/15 11:55:51 11860 /cougar/custom/switch/cpu_mux/epld/cpu_mux.jed 98/07/30 11:02:45 19687 /cougar/custom/switch/cid_mux2/xilinx/cid_mux2_r.bit 1998/12/03 09:11:03 50888 /cougar/custom/switch/ovc_mux2/xilinx/ovc_mux2_r.bit 1998/12/03 09:11:03 50888 /cougar/custom/switch/ovc_mux2/xilinx/ovc_mux2_r.bit 98/07/30 11:02:45 19687 /cougar/custom/switch/cid_mux2/xilinx/cid_mux2_r.bit 98/08/07 15:56:50 20666 /cougar/custom/switch/ext_log2/xilinx/ext_log2_r.bit 98/06/11 16:56:44 49904 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit #End-Of-Header
Details for Switch Feature card Image on slot: 5
Functional Version of the FPGA Image: 4.17 #Jtag-Distribution-Format-B #HardwareRequired: 103(2.2-100,3.0-100,4.0-100)
#FunctionalVersion: 4.17 #Sections: 1 #Section1Format: MOTOROLA_EXORMAX Copyright (c) 1996-99 by cisco Systems, Inc. All rights reserved. generated by: gachan on: Fri Apr 9 11:27:38 PDT 1999 using: /cougar/bin/jtag_script Version 1.10 config file: cfc.jcf Chain description: Part type Bits Config file xc4036 3 /cougar/custom/cfc/hermes3/syn/hermes3_r.bit xc4036 3 /cougar/custom/cfc/stat_fpga/xilinx/stat_fpga_r.bit xc4036 3 /cougar/custom/cfc/stat_fpga/xilinx/stat_fpga_r.bit xc4036 3 /cougar/custom/cfc/upc_fpga/xilinx/upc_fpga_r.bit xc4036 3 /cougar/custom/cfc/upc_fpga/xilinx/upc_fpga_r.bit xc4005 3 /cougar/custom/cfc/fc_write/xilinx/wechip_r.bit XC4005 3 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit Number devices = 7 Number of instruction bits = 21 FPGA config file information: Bitgen date/time Sum File 1999/04/06 18:32:24 34981 /cougar/custom/cfc/hermes3/syn/hermes3_r.bit 1999/01/15 15:47:44 46556 /cougar/custom/cfc/stat_fpga/xilinx/stat_fpga_r.bit 1999/01/15 15:47:44 46556 /cougar/custom/cfc/stat_fpga/xilinx/stat_fpga_r.bit 99/04/09 10:56:07 56276 /cougar/custom/cfc/upc_fpga/xilinx/upc_fpga_r.bit 99/04/09 10:56:07 56276 /cougar/custom/cfc/upc_fpga/xilinx/upc_fpga_r.bit 98/02/09 11:58:40 57163 /cougar/custom/cfc/fc_write/xilinx/wechip_r.bit 98/06/11 16:56:44 49904 /cougar/custom/common/jtcfg/xil/jtcfg_r.bit #End-Of-Header
For detailed FPGA image upgrade instructions, see the "Maintaining Functional Images" section in the "Managing Configuration Files, System Images, and Functional Images" chapter of the ATM Switch Router Software Configuration Guide.
 | Caution FPGA image download can not be reverted back once the download is started. Do not interrupt the download procedure. Wait until it has finished before attempting any commands on the switch. Confirm that the download is done in binary mode and check file sizes before and after download. A failure during reprogramming can result in the card being unusable. |
This section contains listings of the caveats for this feature card FPGA functional image.
Use the table to determine if a particular caveat applies to your FPGA functional image release, or if a particular caveat was corrected in your FPGA or firmware image release. These caveats are described in detail in the following section "Resolved Caveats."
Table 1 lists the known caveats and corrected caveats for this feature card FPGA image.
| DDTS Number | FPGA Release | |
|---|---|---|
| Corrected | Caveat | |
CSCdk92832 | x |
|
This section describes the resolved caveats for this feature card FPGA functional image:
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Posted: Fri Aug 25 09:51:04 PDT 2000
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